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Samsung S3C6400 RISC MicroprocessorSimplified Technical Specifications
| Type: |
S3C6400 |
| Manufacturer: |
Samsung |
| Year Released: |
2007 |
Characteristics |
| CPU Structure (complexity): |
RISC |
| Width of Machine Word: |
32 bit |
| Primary (RAM) Data bus: |
32 bit |
Instruction Set |
| Supported Instruction Set(s): |
ARMv6 |
| CPU Core: |
ARM1176JZF-S |
Caches |
| Level 1 cache: |
16KiB data cache / 16 KiB instruction cache |
Technology |
| Semiconductor Technology: |
CMOS |
Additional Details |
| Special Features: |
16/16KB I/D TCM, 2D Graphics Acceleration, ARM TrustZone |
| Related Page: |
http://www.samsung.com/products/semiconductor/MobileSoC/ApplicationProcessor/ARM11Series/S3C6400/S3C6400.htm |
| Datasheet Time: |
May 26, 07 16:11:05 |
| Datasheet Views: |
13845 views |
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