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Samsung S5L8900 RISC SoCSimplified Technical Specifications
| Type: |
S5L8900 |
| Manufacturer: |
Samsung |
| Year Released: |
2007 |
Characteristics |
| CPU Structure (complexity): |
RISC |
| Width of Machine Word: |
32 bit |
| Primary (RAM) Data bus: |
32 bit |
Instruction Set |
| Supported Instruction Set(s): |
ARMv6 |
| CPU Core: |
ARM1176JZF-S |
Clock Frequencies |
| Recommanded Minimum Clock Frequency: |
400 MHz |
| Recommanded Maximum Clock Frequency: |
667 MHz |
Caches |
| Level 1 cache: |
16KiB data cache / 16 KiB instruction cache |
Technology |
| Semiconductor Technology: |
CMOS |
| Minimum Feature Size: |
90 nm |
Additional Details |
| Special Features: |
8-stage integer pipeline, ARM TrustZone, 16/16KB I/D TCM, PowerVR MBX Lite 3D graphics coprocessor (60MHz), vector floating point coprocessor (VPU), 128MB DDR SDRAM integrated |
| Related Page: |
http://www.samsung.com/products/semiconductor/MobileSoC/ApplicationProcessor/ |
| Datasheet Time: |
Nov 8, 07 16:04:46 |
| Datasheet Views: |
19856 views |
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