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Ingenic Jz4755 RISC Microprocessor with embedded DSPSimplified Technical Specifications
| Type: |
Jz4755 |
| Manufacturer: |
Ingenic |
| Year Released: |
2009 |
| Predecessor: |
32bit Ingenic Jz4740 |
Characteristics |
| CPU Structure (complexity): |
RISC |
| Width of Machine Word: |
32 bit |
| Primary (RAM) Data bus: |
32 bit |
| Secondary (ROM) Data bus: |
32 bit |
Instruction Set |
| Supported Instruction Set(s): |
MIPS I, MIPS II |
| CPU Core: |
MIPS XBurst |
Clock Frequencies |
| Recommanded Minimum Clock Frequency: |
360 MHz |
| Recommanded Maximum Clock Frequency: |
400 MHz |
Caches |
| Level 1 cache: |
16KiB data cache / 16 KiB instruction cache |
Technology |
| Semiconductor Technology: |
CMOS |
| Minimum Feature Size: |
160 nm |
| Contacts: |
176 pins |
| Supply Voltage: |
1.8 V |
Additional Details |
| Special Features: |
dual core CPU, XBurst 8-stage pipeline micro-architecture, XBurst SIMD instruction set to support multimedia acceleration, XBurst CPU for video processing, SDRAM controller, NAND flash controller, 8 ch. DMC, Multimedia accelerator, LCD Controller, MMC/SD/SDIO controller, camera interface, 802.3 compliant Ethernet interface |
| Related Page: |
http://www.ingenic.cn/eng/productServ/AppPro/JZ4755/pfCustomPage.aspx |
| Datasheet Time: |
Nov 7, 09 0:31:33 |
| Datasheet Views: |
3373 views |
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