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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component ARM
Type 7TDMI-S Core
Year Released 1997
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv4T
Type of processor core(s)Type and allocation of processor core(s) ARM7TDMI
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  No


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency N/A

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 8 Kbyte I-Cache

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
8KB unified cache, 26/32-bit addressing, MMU, LCD controller, UART, Advanced Microcontroller Bus Architecture (AMBA)

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2007-09-03 22:14
 
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