PhoneDB - infinitely detailed




FacebookGoogle PlusRSS FeedTwitter

Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Centrality
Type Atlas II
Year Released 2005
FunctionMain function of the component  SoC

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv5TEJ
Type of processor core(s)Type and allocation of processor core(s) ARM926EJ-S
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  No


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency N/A

Cache MemoriesCache Memories: 

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
integrated 22 channels Centrality GPS V3 DSP, Jazelle DBX

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2007-09-08 19:01
 
You are here: Processor Specs \ Centrality Atlas II