 Generel Characteristics:
|
Designer |
ARM |
| Type: |
Cortex-A15 MPcore |
| Codename: |
Eagle |
| Year Released: |
2010 |
| Function |
Multi-core Application Processor |
 Architecture:
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): |
ARMv7-A |
| Number of processor core(s): |
4 |
| Type of processor core(s) |
4x ARM Cortex-A15 MPcore |
 Buses:
|
| Memory Interface(s): |
Yes |
| Data Bus Width |
128 bit |
| Number of data bus channels: |
1 ch |
| Non-volatile Memory Interface |
No |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
2500 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
32 Kbyte I-Cache |
| L1 Data Cache per Core |
32 Kbyte D-Cache |
 Technology and Packaging:
|
| Semiconductor Technology: |
CMOS |
 Graphical Subsystem:
|
| Embedded GPU |
N/A |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Communication Interfaces:
|
| Supported USB Specification: |
No |
| Bluetooth support |
No |
| Wireless LAN support |
No |
| Supported Audio/Video Interface: |
No |
 Satellite Navigation:
|
| Supported GPS protocol(s): |
No |
 Additional Information:
|
Special Features:
up to 4x Cortex-A15 Harvard Superscalar processor core, Configurable per processor L1 (up to 32KB+32KB) and common L2 (up to 4MB) cache sizes, VFPv4 FPU, MMU, 128bit AMBA 4 Advanced Coherent Bus, Snopp Control Unit, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT + DBX, ARM CoreSight Multi-core debug and trace function |
 Datasheet Attributes:
|
| Related Page: |
URL |
| Data Integrity |
Preliminary |
| Added |
2010-09-19 20:15 |
All details | 
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