Generel Characteristics: |
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Designer | ARM |
Type: | Cortex-A12 MPCore |
Year Released: | 2013 |
Function | Multi-core Application Processor |
Architecture: |
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Width of Machine Word | 32 bit |
Supported Instruction Set(s): | ARMv7-A |
Type of processor core(s) | 4x ARM Cortex-A12 MPcore |
Number of processor core(s): | quad-core |
Buses: |
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Memory Interface(s): | Yes |
Data Bus Width | 128 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface | No |
Clock Frequencies: |
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Recommended Maximum Clock Frequency: | 2500 MHz max. |
Cache Memories: |
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L1 Instruction Cache per Core | 64 Kbyte I-Cache |
L1 Data Cache per Core | 32 Kbyte D-Cache |
Total L2 Cache | 8192 Kbyte L2 |
Technology and Packaging: |
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Feature Size | 28 nm |
Semiconductor Technology: | CMOS |
Graphical Subsystem: |
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Embedded GPU | N/A |
Cellular Communication: |
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Supported Cellular Data Links | No |
Additional Information: |
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Special Features: up to 4x Cortex-A12 Harvard Superscalar processor core, Configurable per processor L1 (32 or 64 Kbyte I-cache, 32 Kbyte D-cache) and common L2 (256 Kbyte ... 8 Mbyte) cache sizes, VFPv4 FPU, ARMv7 MMU, SCU, LPAE, 128bit AMBA 4 AXI.. ›› |
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Datasheet Attributes: |
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Data Integrity | Preliminary |
Added | 2013-06-07 16:49 |
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