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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Qualcomm
Type Snapdragon 800 MSM8974AB v2
Year Released 2013
FunctionMain function of the component  Multi-core Application Processor with Modem

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 11 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) 4x Qualcomm Krait 400
Number of processor core(s) quad-core

BusesBuses: 
Memory Interface(s):   LPDDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 933 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 14.93 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  eMMC 5.0 , SATASATA revision 1.0 (2003) offering 1.5 Gbit/s data rate , SATA IISerial AT Attachment revision 2.0 (released in 2004) or 2.x offering 3 Gbit/s data rate


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2265 MHz max.

Cache MemoriesCache Memories: 
L0 Instruction Cache per CoreCapacity of level 0 instruction cache per processor core 4 Kbyte L0 I-Cache
L0 Data Cache per CoreCapacity of level 0 data cache per processor core 4 Kbyte L0 D-Cache
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 2048 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Qualcomm Adreno 330 GPU
GPU Clock 550 MHz GPU
Dedicated Graphics MemoryDedicated operative memory (video RAM, VRAM) 1 MiB

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  CSDCircuit Switched Data (CSD) is the original data link protocol of GSM. Up to 9600bit/s download speed , GPRSGeneral Packet Radio Service , EDGEEnhanced Data Rates for GSM Evolution also known as Enhanced GPRS (EGPRS) , UMTSUniversal Mobile Telecommunications System. UMTS Release '99 data link layer, W-CDMA grants up to 384 kbit/s pocket-switched download speed. , HSDPAHigh-Speed Downlink Packet Access is a 3.5G UMTS downlink protocol. , HSPA+ 42.2Single-carrier HSPA+ 42.2 Mbps , CDMA2000 1x , CDMA2000 1xEV-DO , CDMA2000 1xEV-DO Rev A , CDMA2000 1xEV-DO Rev B , TD-SCDMATime Division Synchronous Code Division Multiple Access is the implementation of UMTS  (3G) cellular network in China. , LTELTE (Long Term Evolution) or the E-UTRAN (Evolved Universal Terrestrial Access Network), introduced in 3GPP R8, is the 4G access part of the Evolved Packet System (EPS). , LTE 150/50LTE 151.2 Mbps / 50.4 Mbps (Cat. 4) data links

Additional InformationAdditional Information: 
Special Features
4x Qualcomm Krait 400 Harvard Superscalar processor core, 600 MHz Hexagon QDSP6V5A (GSM, GPRS, EDGE, UMTS/WCDMA HSPA+ 42Mbps, DC-HSPA+, MBMS, LTE Cat. 4, CDMA2000 1xRTT, CDMA2000 1xEV-DO, CDMA2000 1xEV-DO Rev. A, CDMA2000 1xEV-DO Rev. B, CDMA2000 1xEV-DO MC Rev. A,.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2013-09-06 16:45
 
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