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Processor Specs: Referred (not editable) comparison sheet [2]

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Apple A7 APL0698 (S5L8960X)
Apple A8X APL1012 (T7001)
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Apple A7 APL0698  (S5L8960X)
Apple A8X APL1012  (T7001)
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Generel CharacteristicsGenerel Characteristics
Year Released 2013 2014
FunctionMain function of the component SoC SoC

ArchitectureArchitecture
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit 64 bit
Supported Instruction Set(s) ARMv8 (A32, A64) ARMv8-A (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 2x Apple Cyclone cores 3x Apple Typhoon cores
Number of processor core(s) dual-core tri-core

BusesBuses
Memory Interface(s) LPDDR3 SDRAM LPDDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 667 MHz 800 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit 64 bit
Number of data bus channels 1 ch 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 10.67 Gbyte/s 25.6 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory moviNAND, NAND Flash Interface, SATA eMMC 5.1, moviNAND, NAND Flash Interface, SATA

Clock FrequenciesClock Frequencies
Recommended Maximum Clock Frequency 1400 MHz max. 1500 MHz max.

Cache MemoriesCache Memories
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 64 Kbyte I-Cache 64 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 64 Kbyte D-Cache 64 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 1024 Kbyte L2 2048 Kbyte L2
Total L3 Cache 4096 Kbyte L3 4096 Kbyte L3



Technology and PackagingTechnology and Packaging
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm 20 nm
Semiconductor Technology CMOS CMOS
Number of Transistors Integrated 1000000000 3000000000
FabPlant which fabricates the semiconductor component Samsung TSMC

Graphical SubsystemGraphical Subsystem
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). IMG PowerVR G6430 GPU
Number of GPU cores 4-core GPU

Cellular CommunicationCellular Communication

Additional InformationAdditional Information
Special Features 2x Custom Apple Cyclone 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, 4 Mbyte L3 cache, ARM VFPv4, LPDDR3-1333 SDRAM interface, embedded 1 GB LP-DDR3 SD RAM, NAND flash, moviNAND, SATA, eMMC interface, embedded GPS module, HDMI, 1080p video encode, 1080p.. 3x Custom Apple Typhoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, 512 Kbyte L2 cache per core, 4 Mbyte L3 cache, ARM VFPv4, dual-channel 64-bit 800 MHz LP-DDR3-1600 SDRAM interface (25.6 Gbyte/sec), embedded 2 Gbyte LP-DDR3 SD RAM, NAND flash,..

Datasheet AttributesDatasheet Attributes
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b Preliminary Preliminary
AddedThe exact time of the datasheet addition 2013-08-19 14:27 2014-10-14 12:56

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