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Intel Core 6th Gen i5-6300U (Skylake)

Intel Core 6th Gen i3-6006U (Skylake)

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Generel Characteristics

Year Released

2015

2016

Function Main function of the component

Multi-core Application Processor

Architecture

Width of Machine Word Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.

64 bit

Supported Instruction Set(s)

IA-64 (x86-64), MMX, SSE, SSE2, SSE3, SSE4, SSE 4.1, SSE 4.2

Type of processor core(s) Type and allocation of processor core(s)

2x Intel Skylake-U

Number of processor core(s)

dual-core

Buses

Memory Interface(s)

DDR3L SDRAM, LPDDR3 SDRAM

Data Bus Width Maximum selectable bit width of primary data bus (RAM) of memory interface

64 bit

Number of data bus channels

2 ch

Non-volatile Memory Interface Interface which determines physical layer towards the NV memory

Yes

Clock Frequencies

Recommended Minimum Clock Frequency

2400 MHz min.

Recommended Maximum Clock Frequency

3000 MHz max.

2000 MHz max.

Cache Memories

L1 Instruction Cache per Core Capacity of level 1 instruction cache per processor core

32 Kbyte I-Cache

L1 Data Cache per Core Capacity of level 1 data cache per processor core

32 Kbyte D-Cache

Total L2 Cache Capacity of level 2 cache shared between processor core(s)

512 Kbyte L2

Total L3 Cache

3072 Kbyte L3

Technology and Packaging

Feature Size The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology

14 nm

Semiconductor Technology

CMOS

Fab

Intel

Pins

1356 pins

Graphical Subsystem

Embedded GPU Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).

Intel Iris Graphics 520 GPU

GPU Clock

300 MHz GPU

Cellular Communication

Additional Information

Special Features

Dual Intel Core i5 Skylake-U processor cores, 32 Kbyte instruction cache per core, 32 Kbyte data cache per core, 256 Kbyte L2 cache per core, 3 Mbyte L3 cache (Intel Smart Cache), dual-channel 64-bit DDR4-2133, LPDDR3-1866, DDR3L-1600 SD RAM interface..

Datasheet Attributes

Data Integrity Data integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b

Preliminary

Added

2015-10-08 14:28

2016-12-06 23:10