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Apple A9 APL0898 (S8000)

Apple A11 Bionic APL1072 / APL1W72 (T8015)

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Generel Characteristics

Year Released

2015

2017

Function Main function of the component

Multi-core Application Processor

SoC

Architecture

Width of Machine Word Maximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors.

64 bit

Supported Instruction Set(s)

ARMv8-A (A32, A64)

Pipeline Stages Pipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions.

14 pipeline stages

Type of processor core(s) Type and allocation of processor core(s)

2x Apple Twister cores

2x Apple Monsoon + 4x Apple Mistral cores

Number of processor core(s)

dual-core

hexa-core

Buses

Memory Interface(s)

LPDDR4 SDRAM

LPDDR4x SDRAM

Max. Clock Frequency of Memory IF Clock frequency of fastest supported memory interface

1600 MHz

2064 MHz

Data Bus Width Maximum selectable bit width of primary data bus (RAM) of memory interface

32 bit

64 bit

Number of data bus channels

2 ch

Max. Data Rate Maximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units.

25.6 Gbyte/s

66.05 Gbyte/s

Non-volatile Memory Interface Interface which determines physical layer towards the NV memory

eMMC 5.0, moviNAND, NAND Flash Interface, SATA

eMMC 5.1, moviNAND, NAND Flash Interface, SATA

Clock Frequencies

Recommended Maximum Clock Frequency

1840 MHz max.

2376 MHz max.

Cache Memories

L1 Instruction Cache per Core Capacity of level 1 instruction cache per processor core

64 Kbyte I-Cache

L1 Data Cache per Core Capacity of level 1 data cache per processor core

64 Kbyte D-Cache

Total L2 Cache Capacity of level 2 cache shared between processor core(s)

3072 Kbyte L2

8192 Kbyte L2

Total L3 Cache

4096 Kbyte L3

Technology and Packaging

Feature Size The minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology

14 nm

10 nm

Semiconductor Technology

CMOS

Number of Transistors Integrated

4300000000

Fab

Samsung

TSMC

Graphical Subsystem

Embedded GPU Manufactuer (or IP designer) and type of embedded graphics coprocessor(s).

IMG PowerVR GT7600 GPU

Number of GPU cores

6-core GPU

3-core GPU

GPU Clock

650 MHz GPU

Cellular Communication

Additional Information

Special Features

2x Custom Apple Twister 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, HMP, ARM VFPv4, 4 Mbyte (victim) L3 cache, HDMI, 2160p video encode, 2160p video decode, OpenCL 1.2, OpenGL, Vulkan, DirectX 11

TMHS09, 2x high-performance Apple Monsoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores + 4x high-efficiency Apple Mistral 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, HMP, ARM VFPv4, 2 / 3 Gbyte embedded LP-DDR4x SD RAM, HDMI, 2160p video encode,..

Datasheet Attributes

Data Integrity Data integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b

Preliminary

Added

2015-09-07 10:57

2017-09-12 23:54