ARM Cortex-A8 datasheet

Generel Characteristics:
Designer	ARM
Type:	Cortex-A8
Year Released:	2005
Function	Application Processor
Collapse datasheet \| Add to compare Architecture:
Width of Machine Word	32 bit
Supported Instruction Set(s):	ARMv7-A
Pipeline Stages	13 pipeline stages
Number of processor core(s):	1
Type of processor core(s)	ARM Cortex
Buses:
Memory Interface(s):	Yes
Data Bus Width	32 bit
Number of data bus channels:	1 ch
Non-volatile Memory Interface	No
Clock Frequencies:
Recommended Maximum Clock Frequency:	N/A
Cache Memories:
L1 Instruction Cache per Core	32 Kbyte I-Cache
L1 Data Cache per Core	32 Kbyte D-Cache
Total L2 Cache	1024 Kbyte L2
Technology and Packaging:
Feature Size	65 nm
Semiconductor Technology:	CMOS
Graphical Subsystem:
Embedded GPU	N/A
Collapse datasheet Cellular Communication:
Supported Cellular Data Links	No
Satellite Navigation:
Supported GPS protocol(s):	No
Additional Information:
Instruction Execution Performance:	2000 million instruction per
Instruction Execution Performance Clock Rate:	1000 MHz
Special Features: Superscalar processor, Configurable L1 and L2 cache sizes, FPU, MMU, AMBA 3.0 AXI bus, NEON Media Processing technology, ARM Thumb-2 Technology, ARM TrustZone Technology, ARM CoreSight, ARM Jazelle RCT
Datasheet Attributes:
Related Page:	URL
Data Integrity	Final
Added	2007-09-04 17:10