 Generel Characteristics:
|
Designer |
SiRF |
| Type: |
atlasV |
| Year Released: |
2010 |
| Function |
Application Processor |
 Architecture:
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): |
ARMv6 |
| Pipeline Stages |
8 pipeline stages |
| Type of processor core(s) |
ARM1136JF-S |
| Number of processor core(s): |
single-core |
 Buses:
|
| Memory Interface(s): |
DDR SDRAM
, LPDDR SDRAM
, DDR2 SDRAM |
| Max. Clock Frequency of Memory IF |
400 MHz |
| Data Bus Width |
64 bit |
| Number of data bus channels: |
1 ch |
| Max. Data Rate |
6.4 Gbyte/s |
| Non-volatile Memory Data Bus Width |
8 bit |
| Non-volatile Memory Interface |
NAND Flash Interface |
 Clock Frequencies:
|
| Recommended Minimum Clock Frequency: |
664 MHz min. |
| Recommended Maximum Clock Frequency: |
500 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
16 Kbyte I-Cache |
| L1 Data Cache per Core |
16 Kbyte D-Cache |
 Technology and Packaging:
|
| Feature Size |
65 nm |
| Semiconductor Technology: |
CMOS |
| Pins |
285 pins |
 Graphical Subsystem:
|
| Embedded GPU |
N/A |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Additional Information:
|
Special Features:
VFPU, MMU, integrated 64-channel SiRF GPS / Galileo engine, USB 2.0 OTG, SiRFAlwaysFix and SiRFHibernation technology technology, I2S, I2C, AC 97 audio, 4 x SD/MMC+/SDIO, 2 UARTs , 2 x I2C, 12-bit ADC |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2010-06-29 16:41 |
All details | 
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