 Generel Characteristics:
|
Designer |
ZiiLABS |
| Type: |
ZMS-05 |
| Year Released: |
2009 |
| Function |
Multi-core Application Processor |
 Architecture:
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): |
ARMv5TEJ |
| Type of processor core(s) |
ARM926EJ-S |
| Number of processor core(s): |
single-core |
 Buses:
|
| Memory Interface(s): |
SDRAM
, DDR SDRAM
, LPDDR SDRAM
, DDR2 SDRAM |
| Data Bus Width |
64 bit |
| Number of data bus channels: |
1 ch |
| Non-volatile Memory Data Bus Width |
32 bit |
| Non-volatile Memory Interface |
NAND Flash Interface
, NOR Flash Interface |
 Clock Frequencies:
|
| Recommended Maximum Clock Frequency: |
666 MHz max. |
 Cache Memories:
|
| L1 Data Cache per Core |
16 Kbyte D-Cache |
 Technology and Packaging:
|
| Semiconductor Technology: |
CMOS |
 Graphical Subsystem:
|
| Embedded GPU |
N/A |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Satellite Navigation:
|
| Supported GPS protocol(s): |
No |
 Additional Information:
|
Special Features:
Dual ARM926EJ-S cores, SIMD Media Processing Array (24 Precessing elements), USB 2.0 OTG, TV encoder, three independent video I/O ports, three SDIO/MMC, I2C, I2S, UARTs, GPIOs, Hi-speed serial, SPDIF, IDE, Ethernet, PLLs and RTC, 2D graphics acceleration, Powerful floating-point 3D.. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Final |
| Added |
2010-07-14 22:28 |
All details | 
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