Ingenic Jz4770 datasheet

Generel Characteristics:
Designer	Ingenic
Type:	Jz4770
Year Released:	2011
Function	Application Processor
Collapse datasheet \| Add to compare Architecture:
Width of Machine Word	32 bit
Supported Instruction Set(s):	MIPS32
Pipeline Stages	8 pipeline stages
Number of processor core(s):	1
Type of processor core(s)	MIPS XBurst
Buses:
Memory Interface(s):	mobile (LP) DDR SDRAM
Data Bus Width	32 bit
Number of data bus channels:	1 ch
Non-volatile Memory Interface	NAND Flash Interface , NOR Flash Interface
DMA Channels	12 ch
Clock Frequencies:
Recommended Maximum Clock Frequency:	1000 MHz max.
Cache Memories:
L1 Instruction Cache per Core	16 Kbyte I-Cache
L1 Data Cache per Core	16 Kbyte D-Cache
Total L2 Cache	256 Kbyte L2
Technology and Packaging:
Feature Size	65 nm
Semiconductor Technology:	CMOS
Pins	379 pins
Supply Voltage:	1.2 V
Graphical Subsystem:
Embedded GPU	Vivante GC860 GPU
GPU Clock:	444 MHz GPU
Collapse datasheet Cellular Communication:
Supported Cellular Data Links	No
Satellite Navigation:
Supported GPS protocol(s):	No
Additional Information:
Special Features: XBurst SIMD instruction set, 8-stage pipeline, 16/32-bit LP-DDR/DDR/DDR2 SD RAM interface, 8/16-bit SRAM interface, NOR Flash SLC/MLC/TLC NAND Flash interface, 4/8/12/16/20/24 bit ECC, SRAM interface, 12-ch DMA, 500MHz Xburst VPU, 1080p HD video decode, 444MHz Vivante GC860 GPU, OpenGL ES2.0 and ES1.0, OpenVG1.1, AC97/I2S/SPDIF, Audio Codec, LCD interface, LVDS, TV Encoder, EPD interface, 16.7MP camera interface, Touch ADC, 1-wire, PCM, I2C, SPI, UART, SIM-IF, SD/MMC/SDIO, USB Host, USB OTG 2.0, TS-IF, GPIO, Ethernet MAC, OTP Slave
Datasheet Attributes:
Related Page:	URL
Data Integrity	Preliminary
Added	2011-12-13 15:05