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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Freescale
Type i.MX535D VV1C
Codename MCIMX535DVV1C
Year Released 2011
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 13 pipeline stages
Number of processor core(s) 1
Type of processor core(s)Type and allocation of processor core(s) ARM Cortex-A8

BusesBuses: 
Memory Interface(s):   DDR2 SDRAM , mobile (LP) DDR2 SDRAM , DDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 400 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 3.2 Gbyte/s
Non-volatile Memory Data Bus WidthMaximum selectable bit width of secondary data (non-volatile storage) bus of memory interface 16 bit
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  NOR Flash Interface
DMA ChannelsDMA (Direct Memory Access) allows direct data transfer between operative memory (RAM) and peripherals (hard disk, non-volatile storage, etc.) bypassing processor core. Multiple DMA channels allows parallel DMA operations. 1 ch


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 800 MHz min.
Recommended Maximum Clock Frequency 1000 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 256 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component Freescale
PinsNumber of pins on the package 529 pins
Supply Voltage 1.4 V

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features 128KB shared SRAM, MMU, Smart DMA, ARM NEON SIMD engine, ARM TrustZone, 64-bit AMBA AXI v1.0 bus, 32-bit AMBA AHB 2.0 bus, vector floating point (VFP-Lite), 16/32-bit DDR2-800, LV-DDR2-800, DDR3-800, 32-bit LPDDR2 RAM interface, 8/16-bit NAND SLC/MLC Flash , 4/8/14/16-bit ECC, 8/16-bit NOR Flash, PSRAM, and cellular RAM interface, GPU3D 3D graphics processing unit (256 Kbyte RAM), OpenGL ES 2.0, GPU2D 2D graphics accelerator, OpenVG 1.1, PATA, SATA interface, HDMI interface (1080p60), SPDIF, 10/100 Ethernet controller

Datasheet AttributesDatasheet Attributes: 

Related Page URL
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2012-02-04 12:30
 
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