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Designer![]() |
NVIDIA |
Type: | Tegra 3 T30L |
Codename: | Kal-El |
Year Released: | 2011 |
Function![]() |
Multi-core Application Processor |
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Width of Machine Word![]() |
32 bit |
Supported Instruction Set(s): | ARMv7-A |
Pipeline Stages![]() |
8 pipeline stages |
Type of processor core(s)![]() |
5x ARM Cortex-A9 MPCore |
Number of processor core(s): | penta-core |
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Memory Interface(s): | LPDDR2 SDRAM , DDR3L SDRAM |
Max. Clock Frequency of Memory IF![]() |
667 MHz |
Data Bus Width![]() |
32 bit |
Number of data bus channels: | 1 ch |
Max. Data Rate![]() |
5.34 Gbyte/s |
Non-volatile Memory Interface![]() |
NAND Flash Interface |
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Recommended Maximum Clock Frequency: | 1300 MHz max. |
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L1 Instruction Cache per Core![]() |
32 Kbyte I-Cache |
L1 Data Cache per Core![]() |
32 Kbyte D-Cache |
Total L2 Cache![]() |
1024 Kbyte L2 |
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Feature Size![]() |
40 nm |
Semiconductor Technology: |
CMOS![]() |
Fab![]() |
TSMC |
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Embedded GPU![]() |
NVIDIA GeForce ULP MP12 GPU |
Number of GPU cores: | 12-core GPU |
GPU Clock: | 416 MHz GPU |
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Supported Cellular Data Links![]() |
No |
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Supported GPS protocol(s): | No |
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Special Features: 4x Cortex-A9 Harvard Superscalar primary core, 1x 500MHz Cortex-A9 Harvard Superscalar companion core, 32KB I-cache + 32KB D-cache per core, 1MB L2 cache in total, 32-bit LP-DDR2-1066 and DDR3-L-1333 SD RAM interface, ARM NEON instruction set, Enhanced NAND Flash support,.. ›› |
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Data Integrity![]() |
Preliminary |
Added![]() |
2012-02-27 20:40 |
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