Generel Characteristics: |
Designer |
NVIDIA |
Type: |
Tegra 4i SP3X |
Codename: |
Grey |
Year Released: |
2014 |
Function |
Multi-core Application Processor with Modem |
Architecture: |
Width of Machine Word |
32 bit |
Supported Instruction Set(s): |
ARMv7-A |
Pipeline Stages |
8 pipeline stages |
Type of processor core(s) |
5x ARM Cortex-A9-R4 MPCore |
Number of processor core(s): |
penta-core |
Buses: |
Memory Interface(s): |
LPDDR2 SDRAM
, LPDDR3 SDRAM |
Max. Clock Frequency of Memory IF |
800 MHz |
Data Bus Width |
32 bit |
Number of data bus channels: |
1 ch |
Max. Data Rate |
6.4 Gbyte/s |
Non-volatile Memory Interface |
Yes |
Clock Frequencies: |
Recommended Minimum Clock Frequency: |
1200 MHz min. |
Recommended Maximum Clock Frequency: |
2300 MHz max. |
Cache Memories: |
L1 Instruction Cache per Core |
32 Kbyte I-Cache |
L1 Data Cache per Core |
32 Kbyte D-Cache |
Total L2 Cache |
1024 Kbyte L2 |
Technology and Packaging: |
Feature Size |
28 nm |
Semiconductor Technology: |
CMOS |
Fab |
TSMC |
Graphical Subsystem: |
Embedded GPU |
NVIDIA GeForce ULP MP60 GPU |
Number of GPU cores: |
60-core GPU |
GPU Clock: |
600 MHz GPU |
Cellular Communication: |
Supported Cellular Data Links |
CSD
, GPRS
, HSUPA
, HSUPA 5.8
, HSDPA
, HSPA+ 42.2
, TD-SCDMA
, TD-HSDPA
, LTE
, LTE 100/50
, LTE 150/50 data links |
Additional Information: |
Special Features: 4x Cortex-A9-R4 Harvard Superscalar primary cores, 1x Cortex-A9 Harvard Superscalar companion core, ARM NEON instruction set, integrated NVIDIA Icera i500 cellular modem (GSM, GPRS, HSPA+ 42.2 Mbps, HSUPA 5.76 Mbps, TD-SCDMA, TD-HSPA, TD-LTE, LTE Cat. 3., LTE Cat. 4), 1920x1080.. ›› |
Datasheet Attributes: |
Data Integrity |
Preliminary |
Added |
2013-02-24 12:52 |