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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component ARM
Type Cortex-A12 MPCore
Year Released 2013
FunctionMain function of the component  Multi-core Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7-A
Type of processor core(s)Type and allocation of processor core(s) 4x ARM Cortex-A12 MPcore
Number of processor core(s) quad-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 128 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  No


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2500 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 64 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 8192 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 28 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). N/A

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features
up to 4x Cortex-A12 Harvard Superscalar processor core, Configurable per processor L1 (32 or 64 Kbyte I-cache, 32 Kbyte D-cache) and common L2 (256 Kbyte ... 8 Mbyte) cache sizes, VFPv4 FPU, ARMv7 MMU, SCU, LPAE, 128bit AMBA 4 AXI.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2013-06-07 16:49
 
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