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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Allwinner
Type A10
Year Released 2012
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv7
Pipeline StagesPipeline is kind of instruction level parallelism where stages (FETCH, DEC, OP, EXEC, RES, etc.) of instruction execution are separeted and parallelized between neighboring instructions. 13 pipeline stages
Type of processor core(s)Type and allocation of processor core(s) ARM Cortex-A8
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   LPDDR2 SDRAM , LPDDR3 SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  NAND Flash Interface


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency N/A

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 32 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 32 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 256 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). ARM Mali-400 GPU
Dedicated Graphics MemoryDedicated operative memory (video RAM, VRAM) 0.25 MiB

Cellular CommunicationCellular Communication: 

Supported Cellular Data LinksList of supported cellular data links  No

Satellite NavigationSatellite Navigation: 

Supported GPS protocol(s):   No

Additional InformationAdditional Information: 
Special Features ARM Cortex-A8 Harvard Superscalar processor core, 32-bit .. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2013-06-12 18:27
 
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