Generel Characteristics:
|
Designer |
Apple |
Type: |
A8X APL1012 |
Codename: |
T7001 |
Year Released: |
2014 |
Function |
SoC |
Architecture:
|
Width of Machine Word |
64 bit |
Supported Instruction Set(s): |
ARMv8-A (A32, A64) |
Type of processor core(s) |
3x Apple Typhoon cores |
Number of processor core(s): |
tri-core |
Buses:
|
Memory Interface(s): |
LPDDR3 SDRAM |
Max. Clock Frequency of Memory IF |
800 MHz |
Data Bus Width |
64 bit |
Number of data bus channels: |
2 ch |
Max. Data Rate |
25.6 Gbyte/s |
Non-volatile Memory Interface |
eMMC 5.1
, moviNAND
, NAND Flash Interface
, SATA |
Clock Frequencies:
|
Recommended Maximum Clock Frequency: |
1500 MHz max. |
Cache Memories:
|
L1 Instruction Cache per Core |
64 Kbyte I-Cache |
L1 Data Cache per Core |
64 Kbyte D-Cache |
Total L2 Cache |
2048 Kbyte L2 |
Total L3 Cache: |
4096 Kbyte L3 |
Technology and Packaging:
|
Feature Size |
20 nm |
Semiconductor Technology: |
CMOS |
Number of Transistors Integrated: |
3000000000 |
Fab |
TSMC |
Graphical Subsystem:
|
Embedded GPU |
N/A |
Cellular Communication:
|
Supported Cellular Data Links |
No |
Satellite Navigation:
|
Supported GPS protocol(s): |
Yes |
Additional Information:
|
Special Features: 3x Custom Apple Typhoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores, 512 Kbyte L2 cache per core, 4 Mbyte L3 cache, ARM VFPv4, dual-channel 64-bit 800 MHz LP-DDR3-1600 SDRAM interface (25.6 Gbyte/sec), embedded 2 Gbyte LP-DDR3 SD RAM, NAND flash,.. ›› |
Datasheet Attributes:
|
Data Integrity |
Preliminary |
Added |
2014-10-14 12:56 |