Generel Characteristics: |
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Designer | NEC |
Type: | VR4305 |
Year Released: | 1998 |
Function | Application Processor |
Architecture: |
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Width of Machine Word | 64 bit |
Supported Instruction Set(s): | MIPS I, MIPS II, MIPS III |
Pipeline Stages | 5 pipeline stages |
Number of processor core(s): | 1 |
Type of processor core(s) | MIPS R4300i |
Buses: |
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Memory Interface(s): | Yes |
Data Bus Width | 64 bit |
Number of data bus channels: | 1 ch |
Non-volatile Memory Interface | No |
Clock Frequencies: |
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Internal Systembus Clock: | 33 MHz |
Recommended Maximum Clock Frequency: | N/A |
Cache Memories: |
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L1 Instruction Cache per Core | 16 Kbyte I-Cache |
L1 Data Cache per Core | 8 Kbyte D-Cache |
Total L2 Cache | 1024 Kbyte L2 |
Technology and Packaging: |
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Semiconductor Technology: | CMOS |
Pins | 120 pins |
Graphical Subsystem: |
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Embedded GPU | N/A |
Cellular Communication: |
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Supported Cellular Data Links | No |
Communication Interfaces: |
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Supported USB Specification: | No |
Bluetooth support | No |
Wireless LAN support | No |
Supported Audio/Video Interface: | No |
Satellite Navigation: |
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Supported GPS protocol(s): | No |
Additional Information: |
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Special Features: 5-stage Pipeline |
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Datasheet Attributes: |
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Data Integrity | Final |
Added | 2006-01-01 06:00 |
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