 Generel Characteristics:
|
Designer |
Intel |
| Type: |
Core M 5th Gen M-5Y71 |
| Codename: |
Broadwell |
| Year Released: |
2014 |
| Function |
Multi-core Application Processor |
 Architecture:
|
| Width of Machine Word |
64 bit |
| Supported Instruction Set(s): |
IA-64 (x86-64), MMX, SSE, SSE2, SSE3, SSE4, SSE 4.1 |
| Type of processor core(s) |
2x Intel Core M |
| Number of processor core(s): |
dual-core |
 Buses:
|
| Memory Interface(s): |
DDR3L SDRAM
, DDR3L-RS SDRAM
, LPDDR3 SDRAM |
| Max. Clock Frequency of Memory IF |
800 MHz |
| Data Bus Width |
64 bit |
| Number of data bus channels: |
2 ch |
| Max. Data Rate |
25.6 Gbyte/s |
| Non-volatile Memory Interface |
Yes |
 Clock Frequencies:
|
| Internal Systembus Clock: |
1200 MHz |
| Recommended Maximum Clock Frequency: |
2900 MHz max. |
 Cache Memories:
|
| L1 Instruction Cache per Core |
32 Kbyte I-Cache |
| L1 Data Cache per Core |
32 Kbyte D-Cache |
| Total L2 Cache |
512 Kbyte L2 |
| Total L3 Cache: |
4096 Kbyte L3 |
 Technology and Packaging:
|
| Feature Size |
14 nm |
| Semiconductor Technology: |
CMOS |
| Number of Transistors Integrated: |
1300000000 |
| Fab |
Intel |
| Pins |
1234 pins |
 Graphical Subsystem:
|
| Embedded GPU |
Intel HD Graphics 5300 GPU |
| GPU Clock: |
300 MHz GPU |
 Cellular Communication:
|
| Supported Cellular Data Links |
No |
 Additional Information:
|
Special Features:
Dual Intel Core M processor cores, 32 Kbyte instruction cache per core, 32 Kbyte data cache per core, 256 Kbyte L2 cache per core, 4 Mbyte L3 cache, dual-channel 64-bit 667 MHz / 800 MHz LP-DDR3 / 800 MHz DDR3L/DDR3L-RS.. ›› |
 Datasheet Attributes:
|
| Data Integrity |
Preliminary |
| Added |
2015-01-11 18:16 |
All details | 
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