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Designer![]() |
Intel |
Type: | Core M 6th Gen m5-6Y54 |
Codename: | Skylake |
Year Released: | 2015 |
Function![]() |
Multi-core Application Processor |
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Width of Machine Word![]() |
64 bit |
Supported Instruction Set(s): | IA-32 (x86), IA-64 (x64), SSE4, SSE 4.1, SSE 4.2, AVX 2.0 |
Type of processor core(s)![]() |
2x Intel Skylake-Y |
Number of processor core(s): | dual-core |
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Memory Interface(s): | DDR3L SDRAM , LPDDR3 SDRAM |
Max. Clock Frequency of Memory IF![]() |
933 MHz |
Data Bus Width![]() |
64 bit |
Number of data bus channels: | 2 ch |
Max. Data Rate![]() |
29.86 Gbyte/s |
Non-volatile Memory Interface![]() |
Yes |
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Recommended Minimum Clock Frequency: | 1100 MHz min. |
Recommended Maximum Clock Frequency: | 2700 MHz max. |
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L1 Instruction Cache per Core![]() |
32 Kbyte I-Cache |
L1 Data Cache per Core![]() |
32 Kbyte D-Cache |
Total L2 Cache![]() |
512 Kbyte L2 |
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Feature Size![]() |
14 nm |
Semiconductor Technology: |
CMOS![]() |
Fab![]() |
Intel |
Pins![]() |
1515 pins |
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Embedded GPU![]() |
Intel Iris Graphics 515 GPU |
Number of GPU cores: | 24-core GPU |
GPU Clock: | 300 MHz GPU |
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Supported Cellular Data Links![]() |
No |
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Supported GPS protocol(s): | No |
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Special Features: | Dual Intel Core-M Skylake-Y processor cores, 32 Kbyte.. ›› |
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Data Integrity![]() |
Preliminary |
Added![]() |
2015-11-30 14:53 |
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