|
|
Designer |
Ingenic |
| Type: | M200 |
| Year Released: | 2015 |
| Function |
Application Processor |
|
|
| Width of Machine Word |
32 bit |
| Supported Instruction Set(s): | MIPS32 |
| Pipeline Stages |
9 pipeline stages |
| Type of processor core(s) |
1x MIPS XBurst-HP + 1x MIPS XBurst-LP |
| Number of processor core(s): | dual-core |
|
|
| Memory Interface(s): | LPDDR SDRAM , DDR2 SDRAM , LPDDR2 SDRAM , DDR3 SDRAM |
| Max. Clock Frequency of Memory IF |
667 MHz |
| Data Bus Width |
32 bit |
| Number of data bus channels: | 1 ch |
| Max. Data Rate |
5.34 Gbyte/s |
| Non-volatile Memory Data Bus Width |
64 bit |
| Non-volatile Memory Interface |
NAND Flash Interface |
|
|
| Recommended Maximum Clock Frequency: | 1200 MHz max. |
|
|
| L1 Instruction Cache per Core |
32 Kbyte I-Cache |
| L1 Data Cache per Core |
32 Kbyte D-Cache |
| Total L2 Cache |
512 Kbyte L2 |
|
|
| Semiconductor Technology: |
CMOS |
| Pins |
270 pins |
|
|
| Embedded GPU |
N/A |
| Number of GPU cores: | 1-core GPU |
|
|
| Supported Cellular Data Links |
No |
|
|
| Supported GPS protocol(s): | No |
|
|
| Special Features: | 1x XBurst-HP (1.2GHz) + 1x XBurst-LP (300 MHz).. ›› |
|
|
| Data Integrity |
Preliminary |
| Added |
2018-02-09 15:37 |
| Tweet | |
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