Generel Characteristics: |
|
Designer | Apple |
Type: | A12 Bionic APL1081 / APL1W81 |
Codename: | T8020 |
Year Released: | 2018 |
Function | Multi-core Application Processor |
Architecture: |
|
Width of Machine Word | 64 bit |
Supported Instruction Set(s): | ARMv8.3-A (A32, A64) |
Type of processor core(s) | 2x Apple Vortex + 4x Apple Tempest cores |
Number of processor core(s): | hexa-core |
Buses: |
|
Memory Interface(s): | LPDDR4x SDRAM |
Max. Clock Frequency of Memory IF | 2133 MHz |
Data Bus Width | 16 bit |
Number of data bus channels: | 4 ch |
Max. Data Rate | 34.13 Gbyte/s |
Non-volatile Memory Interface | eMMC 5.1 , moviNAND , NAND Flash Interface , SATA |
Clock Frequencies: |
|
Recommended Maximum Clock Frequency: | 2496 MHz max. |
Cache Memories: |
|
L1 Instruction Cache per Core | 128 Kbyte I-Cache |
L1 Data Cache per Core | 128 Kbyte D-Cache |
Total L2 Cache | 10240 Kbyte L2 |
Total L3 Cache: | 8192 Kbyte L3 |
Technology and Packaging: |
|
Feature Size | 7 nm |
Semiconductor Technology: | FinFET |
Number of Transistors Integrated: | 6900000000 |
Fab | TSMC |
Graphical Subsystem: |
|
Embedded GPU | Apple G11P GPU |
Number of GPU cores: | 4-core GPU |
GPU Clock: | 1125 MHz GPU |
Cellular Communication: |
|
Supported Cellular Data Links | No |
Additional Information: |
|
Special Features: 2x high-performance 3 GHz Apple Vortex 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (128 Kbyte L1 data cache per core, 128Kbyte L1 instruction cache per core) + 4x high-efficiency 1.6 GHz Apple Tempest 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores.. ›› |
|
Datasheet Attributes: |
|
Data Integrity | Preliminary |
Added | 2018-09-13 21:12 |
Tweet | |