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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Apple
Type M1 Pro Lite APL1103 / APL1W03
Codename T6000
Year Released 2021
FunctionMain function of the component  Multi-core Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8.6-A (A32, A64)
Number of processor core(s) 8
Type of processor core(s)Type and allocation of processor core(s) 6x Apple Firestorm + 2x Apple Icestorm cores

BusesBuses: 
Memory Interface(s):   LPDDR5 SDRAM
Address Bus WidthMaximum selectable bit width of address bus of memory interface 32 bit
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 3200 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 128 bit
Number of data bus channels 2 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 204.8 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  eMMC 5.1Complies with embedded MMC 5.1 specification released in 2015 , moviNANDmoviNAND is a multimedia card (MMC) controller and onboard firmware developed by Samsung in 2006 , NAND Flash Interface , SATASATA revision 1.0 (2003) offering 1.5 Gbit/s data rate , SATA IISerial AT Attachment revision 2.0 (released in 2004) or 2.x offering 3 Gbit/s data rate , SATA IIISerial ATA revision 3.0 (released in 2004) or 3.x with 6 Gbit/s data rate , UFS 3.1UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface , UFS 3.1 2-laneComplies with dual-lane Universal Flash Storage 3.1 revision offering 2.9 GB/s NAND flash data rate


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 600 MHz min.
Recommended Maximum Clock Frequency 3228 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 192 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 128 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 22528 Kbyte L2
Total L3 Cache 24576 Kbyte L3

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 5 nm
Semiconductor Technology:   FinFETMultigate (usually double-gate) MOSFET transistor technology
Number of Transistors Integrated 33700000000
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). Apple M1 Pro GPU
Number of GPU cores 14-core GPU
GPU Clock 1296 MHz GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Communication InterfacesCommunication Interfaces: 
Supported USB Specification:   USB 2.0Released in April 2000, USB 2.0 specification introduced USB Hi-Speed enabling devices to communicate at 480 Mbit/s data rate. , USB 3.0 / USB 3.1 Gen 1 / USB 3.2 Gen 1x1Released in November 2008, USB 3.0 specification introduced USB SuperSpeed enabling devices to communicate at 5 Gbit/s. Later renamed as USB 3.1 Gen 1, then  USB 3.2 Gen 1x1 , USB 3.1 Gen 2 / USB 3.2 Gen 2x1Released in July, 2013, USB 3.1 Gen 2 specification introduced USB SuperSpeed+ enabling devices to communicate at 10 Gbit/s data rate. USB 3.1 standard is backward compatible with USB 2.0 and 3.0. Later renamed as USB 3.2 Gen 2x1 , USB 3.2 Gen 1x2Released in 2017, USB 3.2 Gen 1x2 specification introduced 10 Gbit/s dual lane data rate. USB 3.2 Gen 1x2 standard is backward compatible with USB 3.0 , USB 3.2 Gen 2x2Released in 2017, USB 3.2 Gen 2x2 specification introduced 20 Gbit/s dual lane data rate. USB 3.2 Gen 2x2 standard is backward compatible with USB 3.0 , USB4 Gen 2x2Released in 2019, USB4 1.0 specification introduced USB4 Gen 2x2 20 Gbit/s dual lane data rate. USB4 standard is backward compatible with USB 3.2 , USB4 Gen 3x2Released in 2019, USB4 1.0 specification introduced USB4 Gen 3x2 40 Gbit/s dual lane data rate. USB4 standard is backward compatible with USB 3.2
Bluetooth supportThis field specifies the supported BT version  No
Wireless LAN supportThis field enumerates the supported Wi-Fi protocols  No
Supported Audio/Video Interface:   HDMI (Unspecified) , DisplayPort (Unspecified) , HDMI 1.3HDMI 1.3 specification was published June 22, 2006 with increased clock speed up to 340 MHz and resolution up to 2560x1600 at 60fps. , HDMI 1.3aHDMI 1.3a specification was published on November 10, 2006 , HDMI 1.4HDMI 1.4 specification was published May 28, 2009 and introduces HDMI Type D micro connector and 4K video support. , HDMI 1.4aHDMI 1.4a specification was published on March 4, 2010. , HDMI 2.0 (UHD)HDMI 2.0 specification was published on September 4, 2013 with increased clock speed up to 600 MHz and resolution up to 4096x2160 at 60fps.

Satellite NavigationSatellite Navigation: 
Supported GPS protocol(s):   GPS (NMEA 0183)NMEA 0183
Supported Galileo service(s)Galileo is a global satellite  navigation system operated by European Union and the European Space Agency.  Yes
Supported GLONASS protocol(s)GLONASS is a global satellite  navigation system operated by Russia.  Yes
Supported BeiDou system (BDS)BeiDou System (BDS) is a Chinese satellite navigation system. Its global variant is the BeiDou-2 alias COMPASS.  B1IBeiDou-2 (COMPASS) B1I signal transmitted by BDS-2 satellites is centered at 1561.098 MHz, featuring a QPSK(2) modulation BeiDou receiver

Additional InformationAdditional Information: 
Special Features
6x high-performance Apple Firestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 3228 MHz, 192 KiB of L1 instruction cache per core, 128 KiB of L1 data cache per core, 18 MiB shared L2 cache) + 2x high-efficiency Apple Icestorm 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (up to 2064 MHz, 128 KiB L1 instruction cache per core, 64 KiB L1 data cache per core, 4 MiB shared L2 cache), HMP, ARM VFPv4, 16-core NPU, 8K 60 fps HDR video encode, 8K 60 fps HDR video decode, OpenCL, OpenGL, Vulkan, DirectX 12.1

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2022-07-05 15:06
 
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