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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component Samsung
Type Google Tensor G2 GS201 S5P9855
Codename Cloudripper
Year Released 2022
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8.3 (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 2x ARM Cortex-X1 + 2x ARM Cortex-A78 + 4x ARM Cortex-A55 MPcores
Number of processor core(s) octa-core

BusesBuses: 
Memory Interface(s):   LPDDR5 SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit
Number of data bus channels 4 ch
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  UFS 3.1UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2850 MHz max.

Cache MemoriesCache Memories: 
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 3072 Kbyte L2
Total L3 Cache 4096 Kbyte L3

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 5 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component Samsung

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). ARM Mali-G710 GPU
Number of GPU cores 7-core GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  No

Additional InformationAdditional Information: 
Special Features
Dual ARM Cortex-X1 (up to 2.85 GHz) + dual ARM Cortex-A78 (up to 2.35 GHz) + Quad ARM Cortex-A55 (up to 1.8 GHz, 128 Kbyte L2 cache per core) Harvard Superscalar processor cores, tri-cluster HMP, ARM big.LITTLE, 8 Mbyte system.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2023-04-16 22:07
 
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