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Apple A8 APL1011 (T7000)

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Generel Characteristics
DesignerCompany which designed the semiconductor component Apple
Type A8 APL1011
FabPlant which fabricates the semiconductor component TSMC
Codename T7000
Year Released 2014
FunctionMain function of the component SoC

ArchitectureArchitecture
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8-A (A32, A64)
Type of processor core(s)Type and allocation of processor core(s) 2x Apple Typhoon cores
Number of processor core(s) dual-core


BusesBuses
Memory Interface(s) LPDDR3 SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 800 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 64 bit
Number of data bus channels 1 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 12.8 Gbyte/s

Clock FrequenciesClock Frequencies
Recommended Maximum Clock Frequency 1510 MHz max.

Cache MemoriesCache Memories
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 64 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 64 Kbyte D-Cache
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 1024 Kbyte L2

Technology and Packaging
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 20 nm
Semiconductor Technology CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
Number of Transistors Integrated 2000000000

Additional Features
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). IMG PowerVR GX6450 GPU
Number of GPU cores 4-core GPU
Special Features 2x Custom Apple Typhoon 64-bit ARMv8-compatible (AArch32-AArch64) Harvard..


Datasheet Attributes
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b Preliminary
AddedThe exact time of the datasheet addition 2014-08-08 11:30
 
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